In a conventional microprocessor (MPU; Micro Processing Unit, hereinafter simply referred to as a “processor”), a set of processor core (CPU; Central Processing Unit, hereinafter simply referred to as a “core”) formed of an instruction issuing unit or a functional unit is mounted in a package. Recently, microprocessors have entered an era of the so-called “multi-core” or “many-core”, in which a plurality of cores which are independent from each other are mounted in a single package.
This technology is expected to be further developed in the future, and, as a result, it is believed that processors in which many cores are mounted will be developed and cores will find a variety of applications.
In a computer system in which a processor is mounted, an operation called an “interrupt” is executed.
An interrupt means making an interrupt request during program execution. Specifically, an interrupt means suspension of the program execution and execution of an interrupt operation program (interrupt handler).
General operation procedures of this interrupt operation will be explained with reference to FIGS. 5 and 6. FIG. 5 is a block diagram showing an example of a hardware configuration (configuration of a control system in an electronic apparatus (personal computer)) and FIG. 6 is a view showing the procedures of an interrupt operation.
A peripheral apparatus 110 such as a keyboard and a mouse sends an interrupt request to an interrupt controller 120 (Step 102) when an interrupt source is generated (Step 101). Upon receipt of the interrupt request, an interrupt controller 120 sets an interrupt request flag (Step 103). Here, the interrupt controller 120 performs determination of the priority of interrupts for which the flag has been set, masking (determination by a mask register on the validity or the invalidity of the mask) or the like. For unmasked interrupts, an interrupt request signal is sent to a CPU 130 in the order of priority (Step 104).
Upon receipt of the interrupt request signal from the interrupt controller 120, the CPU 130 refers to an interrupt vector by using an interrupt number of the interrupt request signal (Step 105), and the control is transferred to an address written in this interrupt vector, thereby executing an interrupt handler (Step 106).
As mentioned above, in a computer operation, if an interrupt is generated, an interrupt operation is performed by an interrupt vector in such a manner that an on-going operation is suspended.
However, if an interrupt operation is generated, a problem occurs that the operation time is prolonged due to the suspension of the operation. In addition, the cache contents may be rewritten by the interrupt operation, causing the operation speed to be lowered after the normal operation is restored.
Under such circumstances, a technology has been proposed in which an interrupt is performed without lowering the operation speed (see Patent Document 1, for example).
For example, in such a technology, a computer is provided with an operating system (OS), a CPU used only for a normal task operation (normal operation CPU), a CPU used only for an interrupt task operation (interrupt operation CPU) and a memory. When an interrupt occurs during the execution of a normal task by the normal operation CPU, the OS assigns the interrupt CPU according to the interrupt source, allowing the interrupt operation to be executed.
Due to such a configuration, since responding to the interrupt operation only requires a time for assigning an interrupt operation CPU, no time is required for the saving of a program counter or a register, whereby the interrupt operation can be performed more quickly.
Patent Document 1: JP-A-04-033130